`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:01:47 12/07/2013
// Design Name:   IT_BUT_ARRAY
// Module Name:   C:/Users/Jayvee/Desktop/H_264_Decoder/IT_BUT_ARRAY_TEST.v
// Project Name:  H_264_Decoder
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: IT_BUT_ARRAY
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module IT_BUT_ARRAY_TEST;

	// Inputs
	reg DCT_or_HDT;
	reg isDirect;
	reg [15:0] Input_0;
	reg [15:0] Input_1;
	reg [15:0] Input_2;
	reg [15:0] Input_3;
	reg [15:0] Input_4;
	reg [15:0] Input_5;
	reg [15:0] Input_6;
	reg [15:0] Input_7;
	reg [15:0] Input_8;
	reg [15:0] Input_9;
	reg [15:0] Input_10;
	reg [15:0] Input_11;
	reg [15:0] Input_12;
	reg [15:0] Input_13;
	reg [15:0] Input_14;
	reg [15:0] Input_15;

	// Outputs
    /*
    wire [15:0] OneD_0;
	wire [15:0] OneD_1;
	wire [15:0] OneD_2;
	wire [15:0] OneD_3;
	wire [15:0] OneD_4;
	wire [15:0] OneD_5;
	wire [15:0] OneD_6;
	wire [15:0] OneD_7;
	wire [15:0] OneD_8;
	wire [15:0] OneD_9;
	wire [15:0] OneD_10;
	wire [15:0] OneD_11;
	wire [15:0] OneD_12;
	wire [15:0] OneD_13;
	wire [15:0] OneD_14;
	wire [15:0] OneD_15;
    */
	wire [15:0] Output_0;
	wire [15:0] Output_1;
	wire [15:0] Output_2;
	wire [15:0] Output_3;
	wire [15:0] Output_4;
	wire [15:0] Output_5;
	wire [15:0] Output_6;
	wire [15:0] Output_7;
	wire [15:0] Output_8;
	wire [15:0] Output_9;
	wire [15:0] Output_10;
	wire [15:0] Output_11;
	wire [15:0] Output_12;
	wire [15:0] Output_13;
	wire [15:0] Output_14;
	wire [15:0] Output_15;
	reg Clk;
    reg [4:0] cnt;

	// Instantiate the Unit Under Test (UUT)
	IT_BUT_ARRAY uut (
    .DCT_or_HDT(DCT_or_HDT), 
    .isDirect(isDirect), 
    .Input_0(Input_0), 
    .Input_1(Input_1), 
    .Input_2(Input_2), 
    .Input_3(Input_3), 
    .Input_4(Input_4), 
    .Input_5(Input_5), 
    .Input_6(Input_6), 
    .Input_7(Input_7), 
    .Input_8(Input_8), 
    .Input_9(Input_9), 
    .Input_10(Input_10), 
    .Input_11(Input_11), 
    .Input_12(Input_12), 
    .Input_13(Input_13), 
    .Input_14(Input_14), 
    .Input_15(Input_15), 
    /*
    .OneD_0(OneD_0), 
    .OneD_1(OneD_1), 
    .OneD_2(OneD_2), 
    .OneD_3(OneD_3), 
    .OneD_4(OneD_4), 
    .OneD_5(OneD_5), 
    .OneD_6(OneD_6), 
    .OneD_7(OneD_7), 
    .OneD_8(OneD_8), 
    .OneD_9(OneD_9), 
    .OneD_10(OneD_10), 
    .OneD_11(OneD_11), 
    .OneD_12(OneD_12), 
    .OneD_13(OneD_13), 
    .OneD_14(OneD_14), 
    .OneD_15(OneD_15), 
    */
    .Output_0(Output_0), 
    .Output_1(Output_1), 
    .Output_2(Output_2), 
    .Output_3(Output_3), 
    .Output_4(Output_4), 
    .Output_5(Output_5), 
    .Output_6(Output_6), 
    .Output_7(Output_7), 
    .Output_8(Output_8), 
    .Output_9(Output_9), 
    .Output_10(Output_10), 
    .Output_11(Output_11), 
    .Output_12(Output_12), 
    .Output_13(Output_13), 
    .Output_14(Output_14), 
    .Output_15(Output_15)
    );

	initial begin
		// Initialize Inputs
		DCT_or_HDT = 0;
		isDirect = 0;
		Input_0 = 0;
		Input_1 = 0;
		Input_2 = 0;
		Input_3 = 0;
		Input_4 = 0;
		Input_5 = 0;
		Input_6 = 0;
		Input_7 = 0;
		Input_8 = 0;
		Input_9 = 0;
		Input_10 = 0;
		Input_11 = 0;
		Input_12 = 0;
		Input_13 = 0;
		Input_14 = 0;
		Input_15 = 0;
        Clk =0;
        cnt= 0;
		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end

    always #20 Clk=~Clk;
    
    always @(posedge Clk) begin
        case(cnt) 
        0:begin
            cnt <= cnt+1;
            DCT_or_HDT <= 1;
            isDirect <= 0;
            Input_0 <= 1;
            Input_1 <= 2;
            Input_2 <= 3;
            Input_3 <= 4;
            Input_4 <= 5;
            Input_5 <= 6;
            Input_6 <= 7;
            Input_7 <= 8;
            Input_8 <= 9;
            Input_9 <= 10;
            Input_10 <= 11;
            Input_11 <= 12;
            Input_12 <= 13;
            Input_13 <= 14;
            Input_14 <= 15;
            Input_15 <= 16;
        end
        1:begin
            cnt <= cnt;
        end
        default:begin
            cnt <= cnt;
        end
        endcase
    end
    
endmodule

